1. Field of the Invention
The present invention relates to synthesizers. More specifically, the present invention relates to methods and apparatus for reducing spurious frequency errors in Fractional-N type indirect synthesizers.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
Synthesizers are utilized for selecting specific frequencies in the radio spectrum for either transmission or reception of signals. Synthesizers have the ability to step in precise frequency increments. However, indirect, phase-locked single-loop synthesizers cannot provide frequency step sizes less than an applied reference frequency. Further, certain limitations must be satisfied in single-loop synthesizer design in order to provide small frequency step sizes. Those limitations include that the synthesizer must settle at a particular frequency in a very short time and that the synthesizer provide a spectrally pure output (e.g., frequency components and harmonics not included).
To achieve small frequency step sizes, the applied reference frequency (F.sub.ref) must be small since the synthesizer steps in increments of F.sub.ref. In order to achieve a fast settling time at a particular synthesizer frequency, the loop filter must exhibit a wide bandwidth. However, a narrow loop filter bandwidth is required to reject the reference frequency (F.sub.ref) component in the phase detector. These loop filter bandwidth requirements are mutually exclusive. The solution in the past to overcome the inability to provide frequency step sizes smaller than F.sub.ref and to overcome the mutually exclusive bandwidth problems has been to employ fractional-N synthesizers.
A single-loop synthesizer receives the reference frequency (F.sub.ref) signal at the input terminal of a loop phase detector. The output signal of the loop phase detector is transmitted to a low pass loop filter comprised of an operational amplifier and appropriate feedback circuitry. The output of the loop filter is directed to a voltage controlled oscillator (VCO) which provides an output frequency signal. A portion of the output frequency signal is fed back to a loop divider circuit which receives a user-selected program word to program the divide ratio and to provide a divided output frequency signal.
The divided output frequency signal is transmitted to the loop phase detector and compared to F.sub.ref for generating a loop error voltage. The loop error voltage is filtered in the loop filter for tuning the voltage controlled oscillator. Upon being tuned, the voltage controlled oscillator is forced to slew in frequency with the slewed frequency being controlled by the tuned voltage fed into the voltage controlled oscillator. A slewed output frequency signal is fed back to the loop phase detector via the loop divider circuit for reducing the loop error voltage to zero. Thus, the output frequency signal of the voltage controlled oscillator is also the synthesizer output signal. Ideally, the loop error voltage should eventually become zero by the action of the single-loop. The phase detector monitors the changes in the single-loop due to temperature drift and component age that are responsible for changes in the output frequency signal of the voltage controlled oscillator. The error voltage output of the phase detector signals the presence of and compensates for these variations.
The slewed output frequency signal fed back to the loop divider circuit is subjected to division by the user-selected program word "N" which is actually a variable divide ratio "N.sub.div ". The value of "N.sub.div " at any time is controlled by the fractional-N control circuit where "N.sub.div " can assume the value of "N" or "N+1". The fractional-N control circuit comprises an accumulator circuit which includes a latch and an adder. The adder receives a fractional frequency word from an external source. The latch and the adder cooperate with the loop divider to periodically add a "+1" to the program word for changing the divide ratio to "N+1". The use of two dividers provides for an average divide ratio "DIV" effectively having an integer component and a fractional component. However, the instantaneous divide ratio is either "N" of "N+1".
The fractional divide ratio of the fractional-N synthesizer is employed to provide frequency step sizes less than F.sub.ref. This is accomplished by varying the divide ratio over time as illustrated in the following example. To divide by a non-integer value, such as 10.1, the divider would assume the value N=10 for nine cycles in succession and then the value of N+I=11 for one cycle. Over the ten divide intervals, the average ratio is 10.1. Thus, the resulting synthesizer output frequency is 10.1 times the reference frequency F.sub.ref, a fractional multiple.
Since the divider changes between two discrete ratios (N=10, N+1=11), a fractional-N error pulse t.sub.e is created. The output frequency signal from the voltage controlled oscillator is operating at a fractional multiple of F.sub.ref. Dividing by the two ratios "/N" and "/N+1" causes the frequency of the output signal of the loop divider circuit to be somewhat different from the frequency of the constant F.sub.ref being transmitted to the loop phase detector. Although the error pulse t.sub.e is caused by changing the divide ratio in the loop divider, it manifests itself at the output terminal of the loop phase detector. Without correction, the error pulse t.sub.e will result in an undesirable spurious modulation on the synthesizer output signal.
The fractional-N error pulse t.sub.e appears at the output terminal of the phase detector at each reference clock pulse. The error pulse t.sub.e is filtered through the loop filter and generates a voltage error V.sub.err at the input terminal of the voltage controlled oscillator. Since an error pulse t.sub.e appears at the output terminal of the loop phase detector at each clock pulse, the voltage error V.sub.err accumulates over time. The accumulated voltage error V.sub.err modulates the output frequency signal of the voltage controlled oscillator causing spurious signals to appear in the synthesizer output signal. Thus, the fractional-N synthesizer is unable to provide a spectrally pure output signal.
Several attempts have been made to compensate for the existence of the error pulse t.sub.e appearing at the output terminal of the loop phase detector and the corresponding error voltage V.sub.err generated at the input terminal of the voltage controlled oscillator. Generally, the compensation schemes of the prior art include correction circuits which utilize digital-to-analog converters or switched current sources The digital-to-analog approach is limited in that the analog output signal can drift with temperature and result in reduced error pulse cancellation. Current sources, when properly implemented, can provide reasonable insensitivity to temperature variations. However, this solution requires expensive precision components to make the current sources reasonably insensitive to temperature variations. Thus, there are cost and performance disadvantages to both prior art approaches.
Thus, there is a need in the art for an improvement in error pulse correction schemes for single-loop Fractional-N synthesizers which prevent undesirable spurious modulation of the synthesizer output signal.